1. Field of the Invention
The present invention relates to semiconductor devices such as SRAMs (static random access memories), and memory systems and electronic apparatuses equipped with the same.
2. Description of the Related Art
SRAMs are a type of semiconductor memory devices that do not require a refreshing operation and therefore have properties that can simplify the system and lower power consumption. For this reason, SRAMs are widely used as memories for electronic equipment such as mobile phones.
The present invention provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated and which has an improved operation margin for memory cells. The present invention also provides memory systems and electronic apparatuses that include such semiconductor devices.
Additional features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
To achieve the advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a semiconductor device having a memory cell including a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor. The semiconductor device includes a first gate-gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor; and a first drain-gate wiring layer that is continuous with the first gate-gate electrode layer, provided in a manner to extend in a direction transverse to the first gate-gate electrode layer, and provided at least between an active region for the first load transistor and an active region for the first driver transistor. A distance L1 between the edges of the first drain-gate wiring layer and the active region for the first driver transistor is greater than or equal to a distance L2 between the edges of the first drain-gate wiring layer and the active region for the first load transistor.
This structure enables the first driver transistor to be readily fabricated without changing the gate width of the first driver transistor. Accordingly, a first driver transistor having desired characteristics can be readily fabricated, as well as memory cells having desired characteristics.
The present invention also provides for a semiconductor device having a memory cell including a first load transistor, a second load transistor, a first driver transistor, a second driver transistor, a first transfer transistor, and a second transfer transistor. The semiconductor device includes a first gate-gate electrode layer including a gate electrode of the first load transistor and a gate electrode of the first driver transistor; a second gate-gate electrode layer including a gate electrode of the second load transistor and a gate electrode of the second driver transistor; a first drain-gate wiring layer that is continuous with the first gate-gate electrode layer, provided in a manner to extend in a direction transverse to the first gate-gate electrode layer, and provided at least between an active region for the first load transistor and an active region for the first driver transistor; and a contact pad layer that is continuous with the second gate-gate electrode layer, provided in a manner to extend in a direction transverse to the second gate-gate electrode layer, and provided between an active region for the second load transistor and an active region for the second driver transistor. A distance L1 between the edges of the first drain-gate wiring layer and the active region for the first driver transistor is substantially equal to a distance L3 between the edges of the contact pad layer and the active region for the second driver transistor.
By using this structure, a change in the gate length of the first driver transistor and a change in the gate length of the second driver transistor can be made equal to each other even when alignment errors occur in the process. Accordingly, occurrence of a difference in the capability between the first driver transistor and the second driver transistor is reduced. As a result, the operation margin of memory cells can be improved.
In another aspect, the present invention provides a memory system including the above semiconductor device.
In yet another aspect, the present invention provides an electronic apparatus including the above semiconductor device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.